Traffic Light Controller

Designed and implemented a Traffic Light Controller using Verilog HDL, simulating a finite state machine (FSM) approach to manage traffic signals at a four-way intersection.

The controller manages timing sequences for red, yellow, and green lights to ensure smooth traffic flow and pedestrian safety, while being synthesizable for FPGA deployment.

Verified the design through comprehensive testbenches and waveform simulations, ensuring correct state transitions and timing behavior under all traffic conditions.